검색 상세

Electrical Characteristics and Noise Analysis of Multilayer ReS₂ FETs : Influence of Channel Scaling, Thickness, and Electric Field

  • Hyeongjin Choi (최형진, 대학원 전기전자공학과 반도체 및 나노전공)

초록/요약

Since the invention of field-effect transistors (FETs) based on silicon, the size of integrated circuits and FETs has continuously decreased following the trend described by Moore's Law. However, traditional silicon-based FET structures have become increasingly impractical because of short-channel effects. To address this challenge, alternative structures such as dual-gate FETs, FinFETs, and gate-surrounding FETs have been developed. Nonetheless, as the channel length continues to decrease, even these advanced architectures face limitations in maintaining FET performance. This drives the need to investigate alternative materials for replacing silicon. The International Roadmap for Devices and Systems (IRDS) suggests Two-dimensional (2D) materials have gained significant attention as compelling alternatives. Consequently, FETs employing two-dimensional materials have been the subject of extensive investigation. These materials exhibit weak interlayer bonding, leading to variations in electrical properties depending on the number of layers. In comparison with monolayer structures, multilayer configurations demonstrate higher mobility, making them a focal point of FET research. Notable 2D materials include MoS₂, WSe₂, and rhenium disulfide (ReS₂). Among these, ReS₂ stands out because of its exceptionally weak interlayer coupling, which allows it to maintain a direct bandgap that remains unaffected by the number of layers. Consequently, ReS₂-based multilayer FETs have attracted significant research interest. This study analyzes the electrical characteristics of multilayer ReS₂ FETs with respect to scaling. Before presenting the analysis, the fabrication process of multilayer ReS₂ FETs used in this study is described. The methodologies used to extract key electrical parameters such as field-effect mobility, threshold voltage, and interface trap density are introduced, along with three low-frequency noise models. Next, the electrical properties of multilayer ReS₂ FETs with different channel lengths are examined. Devices with channel lengths ranging from 0.25 μm to 4.4 μm, each with a thickness of 8.5 nm, are compared. The results are analyzed using the Thomas-Fermi screening model. For long-channel devices, the channel resistance dominates the overall resistance, leading to the development of a conductive pathway close to the bottom interface region adjacent to the oxide. With shrinking channel lengths, interlayer resistance emerges as a dominant limiting factor in device performance. At low gate voltages, conduction occurs in the bottom region, whereas at high gate voltages, a conductive channel forms at the top side. The impact of drain voltage is also examined. When the drain voltage increases, the bottom-side channel experiences energy band bending under the influence of the electric field generated by the drain bias, resulting in an increase in threshold voltage. For the short-channel device (0.25 μm), at high gate voltages, the conductive channel initially forms at the top side. As the drain voltage increases, interlayer resistance at the drain electrode decreases, shifting the conduction path toward the bottom side. However, increased bottom-side lateral field ultimately facilitates the formation of a top-side channel at a lower gate voltage. Additionally, the electrical behavior of multilayer ReS₂ FETs under high electric fields is investigated. To isolate the effects of high electric fields, two FETs with channel lengths measuring 0.24 μm and 1.5 μm, both with a thickness of 6 nm and sharing a common electrode on the same flake, are compared. Mobility degradation is detected solely in the 0.24 μm device when the drain voltage exceeds 2 V. To determine the underlying cause, a low-frequency noise analysis is performed. Noise waveforms measured as a function of drain voltage are analyzed using the CNF-CMF model and the HMF model, revealing an increase in scattering parameters and Coulomb scattering under high electric fields. The short-channel device (0.25 μm) exhibits significant variations in electrical characteristics with changing drain voltage. This phenomenon arises due to the transition of the conduction channel: at low gate voltages, it forms at the bottom side, while at high gate voltages, it shifts to the top side. Consequently, drain voltage fluctuations induce channel migration, impacting device performance. To mitigate this effect, hexagonal boron nitride (hBN) passivation is applied to the multilayer ReS₂ FETs. The effectiveness of hBN passivation in suppressing drain voltage-induced channel migration is evaluated using transconductance peak analysis and low-frequency noise spectra. The results indicate that hBN passivation increases the threshold voltage and suppresses conduction channel movement in response to drain voltage variations. For long-channel devices (4.4 μm), the conduction channel consistently forms at the bottom region. In contrast, for short-channel devices (0.25 μm), conduction channel initially forms at the bottom region at low gate voltages and transitions to the top region at increased gate voltages. As the channel length is further reduced to below 100 nm, channel resistance becomes less influential, potentially allowing the conduction channel to form directly at the top side after the subthreshold region. To verify this, a multilayer ReS₂ FET with a 50 nm channel length and a 12 nm thickness is fabricated, and its electrical and low-frequency noise characteristics are analyzed. The results confirm that for the 50 nm device, the conduction channel emerges at the top side immediately following the subthreshold regime. Furthermore, with rising drain voltage, the conduction channel progressively moves toward the bottom.

more

목차

ABSTRACT i
국문 초록 iv
TABLE OF CONTENTS viii
LIST OF FIGURES xi
CHAPTER 1. INTRODUCTION 1
1.1 Semiconductor industry and Transition Metal Dichalcogenides (TMDs) 1
1.2 Multilayer ReS2 5
1.3 Outline 6
References 9
CHAPTER 2. Fabrication method, parameter extraction, and low frequency noise model 13
2.1 Fabrication method 13
2.2 Parameter extraction 14
2.2.1 Field effect mobility 14
2.2.2 Threshold voltage 15
2.2.3 Interface trap density 16
2.3 Low frequency noise model 17
2.3.1 CNF (Carrier number fluctuation) model 18
2.3.2 CNF-CMF (Correlated mobility fluctuation) model 18
2.3.3 HMF (Hooge mobility fluctuation) model 19
References 21
CHAPTER 3. The conduction channel characteristics of multilayer ReS2 based on channel scaling 22
3.1 Introduction 22
3.2 Device information 24
3.3 Electrical characteristics of multilayer ReS₂ FETs vs. Channel Length 25
3.4 Relationship between channel length and gate voltage 27
3.5 Relationship between channel length and drain voltage 30
3.6 Conclusion 39
3.7 Measurement results of a thickness multilayer ReS₂ FETs 40
References 42
CHAPTER 4. Electrical property variations of multilayer ReS2 under high-field conditions 45
4.1 Introduction 45
4.2 Device information 46
4.3 Electrical characteristics of multilayer ReS₂ FETs 48
4.4 Low frequency analysis at high electrical field 52
4.5 Conclusion 56
References 57
CHAPTER 5. Mitigating channel migration in multilayer ReS₂ using hBN passivation 61
5.1 Introduction 61
5.2 Device information 62
5.3 Electrical characteristics (before and after hBN passivation) 64
5.4 Low frequency spectra (before and after hBN passivation) 69
5.5 Conclusion 71
References 73
CHAPTER 6. Electrical characteristics of multilayer ReS2 at a 50 nm channel length 76
6.1 Introduction 76
6.2 Device information 77
6.3 Electrical characteristics 79
6.4 Low frequency analysis 86
6.5 Conclusion 88
References 91
CHAPTER 7. CONCLUSION 95
APPENDICES(or SUPPLEMENTARY MATERIALS) 98
A. Memory device using multilayer ReS₂ 98
B. Low freuquency noise analysis of anisotropic multilayer ReS₂ 101

more
반출 Meta View 목록