Energy-Efficient Time-Domain Design Techniques for High-Speed Memory Interfaces
고속 메모리 인터페이스를 위한 에너지 효율적인 시간 영역 설계 기법
- 주제(키워드) Digital phase-locked loop (PLL) , Low-power , Memory interface , Four-level pulse-amplitude modulation (PAM-4) , Single-ended receiver , Sub-sampling
- 발행기관 고려대학교 대학원
- 지도교수 김철우
- 발행년도 2023
- 학위수여년월 2023. 2
- 학위명 박사
- 학과 및 전공 대학원 전기전자공학과
- 세부전공 집적회로
- 세부분야 해당없음
- 원문페이지 95 p
- 실제URI http://www.dcollection.net/handler/korea/000000270247
- UCI I804:11009-000000270247
- DOI 10.23186/korea.000000270247.11009.0001418
- 본문언어 영어
초록/요약
Dynamic random access memory (DRAM) is widely used as main memory in various systems. The bandwidth of DRAM has increased continuously to process a growing amount of data from virtual reality, cloud computing, machine learning, and artificial intelligence. Therefore, energy-efficient design techniques for memory interfaces have become important to increase the DRAM bandwidth. This thesis presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4) receiver with a time-windowed least significant bit (LSB) decoder and a 4 GHz ring-oscillator-based digital sub-sampling phase-locked loop (SSPLL) with a dual-domain phase detector (DDPD) for high-speed memory interfaces. The proposed PAM-4 decoding technique obviates the need for additional comparators and reference voltages that are required in conventional PAM-4 decoders. Same as conventional non-return-to-zero (NRZ) receivers, the proposed PAM-4 receiver uses only one comparator by decoding the LSB through time-windowing the outputs of the comparator that is used to decide a most significant bit (MSB). Therefore, the additional power overhead from a power-hungry analog front-end (AFE) and high-speed clock buffers is minimized in the proposed PAM-4 receiver because it is proportional to the number of comparators. Accordingly, the proposed PAM-4 receiver can achieve superior energy efficiency. Furthermore, the elimination of the use of reference voltages reduces the hardware cost and design complexity. The performance of the digital SSPLL is limited by the quantization noise (Q-noise) of the phase detector (PD), and it requires a large power and area overhead to reduce the Q-noise. The proposed DDPD efficiently detects a phase error in both the voltage- and time-domains, thereby suppressing the Q-noise while minimizing additional cost. It requires only one comparator in the power-hungry digitally-controlled oscillator (DCO) clock path. Consequently, it achieves a high performance while consuming a small amount of power similar to that of a conventional bang-bang phase detector (BBPD). The prototype single-ended PAM-4 receiver and SSPLL were fabricated in a 28-nm complementary metal-oxide-semiconductor (CMOS) technology. The proposed PAM-4 decoding and phase detection techniques improve the performance and the energy-efficiency of high-speed memory interfaces.
more목차
ABSTRACT I
국문 초록 III
TABLE OF CONTENTS V
LIST OF TABLES VII
LIST OF FIGURES VIII
CHAPTER 1. INTRODUCTION 1
1.1 Backgrounds 1
1.2 Thesis Overview 4
CHAPTER 2. CONVENTIONAL WORKS 6
2.1 Conventional Single-Ended Receivers 6
2.2 Conventional PLLs 10
CHAPTER 3. SINGLE-ENDED PAM-4 RECEIVER USING TIME-WINDOWED LSB DECODER 13
3.1 Motivations 13
3.2 Conventional PAM-4 Decoders 15
3.3 Proposed PAM-4 Decoder 18
3.4 Circuit Implementations 26
3.5 Measurement Results 38
CHAPTER 4. SUB-SAMPLING PHASE LOCKED LOOP 46
4.1 Motivations 46
4.2 Conventional Phase Detectors in Digital SSPLLs 49
4.3 Proposed Dual-Domain Phase Detector (DDPD) 51
4.4 Circuit Implementations 59
4.5 Measurements Results 66
CHAPTER 5. CONCLUSION 73
REFERENCES 74
