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MOSFET Layout Optimization and Modeling for Mm-wave and Sub-terahertz Circuits

밀리미터파 및 서브 테라헤르츠 회로를 위한 모스펫 레이아웃 최적화와 모델링

  • Minwoo Kim (김민우, 대학원 전기전자공학과 통신 및 네트워크전공)

초록/요약

In this thesis, MOSFET layout optimization to improve amplifier gain, MOSFET inductance modeling to improve correlation between model and hardware, and D-band low noise amplifier are discussed. Firstly, Layout optimization of multi-finger RF MOSFETs for mm-wave and sub-terahertz circuits is presented. The parasitic capacitance and resistance generated by the interconnect metal of MOSFETs degrade the performance of high-frequency circuits including the gain and frequency bandwidth. The degradation is exacerbated as the frequency increases toward the mm-wave and sub-terahertz band. Fortunately, the adverse effect of the parasitic capacitance can be relieved by circuit design techniques such as the reactive impedance matching and neutralization. However, the parasitic resistance, particularly at the gate, causes loss and gain degradation, which is not easily compensated in the circuit design level. In this work, a layout optimization of the interconnect metal of multi-finger MOSFETs is proposed for minimizing the gate resistance. The optimized MOSFET layout is experimentally observed that the gate resistance is lowered by 10–19.4 % and consequently the device fMAX is improved by 12.6–23.9 % compared to a reference layout. Furthermore, to verify the circuit-level benefit, a D-band single-stage amplifier using the optimized MOSFET layout is demonstrated and compared with an amplifier using the reference layout. The measured peak gain is improved by 1.6 dB at 133 GHz due to the layout optimization. Secondly, MOSFET inductance modeling for improving correlation between model and hardware is presented. Since the parasitic inductance of the MOSFET layout is very small as a few pH, the effect on the circuit operating in a few GHz is negligible. However, as the frequency increases toward the mm-wave and sub-terahertz bands, the effect of parasitic inductance on impedance matching increases. In this work, the parasitic inductance of the MOSFET is extracted and modeled, and additionally verified at the circuit-level. The simulation result of the amplifier to which the parasitic inductance model was applied showed that the operating frequency shifted down by 2.6 GHz compared to that not applied. It is experimentally observed that the correlation between simulation and measurement is improved. Thirdly, a 4-stage low-noise amplifier operating in the D band is presented. The proposed LNA is implemented in a 28-nm bulk CMOS process. To improve gain and noise characteristics, a differential common source structure with capacitance neutralization technique is used. In addition, for wide bandwidth and high gain, the amplifier consists of 4 stages and impedance matching is performed by applying the frequency staggering technique. The LNA exhibits 3-dB bandwidth of 20 GHz and peak gain is 17.8dB at 139GHz. The total chip area including the pad is 0.4 mm2, and the power consumption of the circuit is 50.2 mW.

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목차

CHAPTER 1. INTRODUCTION 1
CHAPTER 2. LAYOUT OPTIMIZATION OF MULTI-FINGER RF MOSFET 3
2.1 Motivation 3
2.2 Device Structure and Analysis 4
2.3 Experimental Results and Discussion 6
2.3.1 Verification in device level 6
2.3.2 Verification in circuit level 11
CHAPTER 3. EXTRACTION AND MODELING OF MOSFET INDUCTANCE 14
3.1 Motivation 14
3.2 Device Structure and Analysis 14
3.3 Experimental Results and Discussion 16
3.3.1 MOSFET Parameters Extraction 16
3.3.2 Verification in circuit level 20
CHAPTER 4. D-BAND LOW NOISE AMPLIFIER 23
4.1 Motivation 23
4.2 Design of Low Noise Amplifier 23
4.2.1 Topology of amplifier 25
4.2.2 Design of core layout 26
4.2.3 Design of input and inter-stage matching network 29
4.3 Experimental Results 30
CHAPTER 5. CONCLUSION 34
REFERENCES 36

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