Optimizing CML-CMOS Converter Through Sizing Transistors for Producing 50% Duty Square Wave
Optimizing CML-CMOS Converter Through Sizing Transistors for Producing 50% Duty Square Wave
- 주제(키워드) CML-CMOS converter , Comparator , Duty , IC , Square wave , VLSI
- 발행기관 한국과학기술원 반도체설계교육센터
- 발행년도 2020
- 총서유형 Journal
- KCI ID ART002647041
- 본문언어 영어
초록/요약
The current-mode logic (CML) circuits are widely used in several ICs for its low power dissipation and high speed performance. As the analog and digital mixed ICs are widely used, this implies great advantage of CML circuits. A drawback of the CML circuit is its less robustness of noises than static CMOS circuits because of its small signal swing. Thus, combined application of CML and static CMOS circuits in a single IC is inevitable, and also the CML-CMOS converter is important to combine them together in a chip. In this paper, by sizing transistors of a comparator, the CML-CMOS converter accomplishes the rail-to-rail output signal with 50.14% duty cycle. Rising/falling time of the output signal are lessened by 87.3~90% compared with input CML signal. D-Q delay of the comparator is optimized by 216~239ps.
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