A 600 GHz Varactor Doubler using CMOS 65nm process
A 600 GHz Varactor Doubler using CMOS 65nm process
- 발행기관 한국과학기술원 반도체설계교육센터
- 발행년도 2016
- 총서유형 Journal
- KCI ID ART002653414
- 본문언어 영어
초록/요약
Varactor and active mode doublers are fabricated and compared in 600 GHz frequency range in terms of output power using CMOS 65nm technology. In designing a frequency multiplier, active mode is generally preferred, since it can provide high conversion efficiency and bandwidth. On the other hands, varactor mode is rarely used when active mode is available because of its severe operation instability, though it can provide high conversion efficiency theoretically. However, in the high frequency range such as 600 GHz band which is far above the cut-off frequency of 65nm NMOSFET, there is possibility that varactor mode outperforms active mode. As a result of measurement, output power of -19.25 dBm is obtained for the varactor mode doubler which is larger than the active mode doubler by the amount of 3.5 - 6 dBm in different measured frequency. The result is fairly acceptable in 600 GHz frequency considering the process technology.
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