Binarized Neural Networks Accelerator Supporting Dynamic Filter Size Based on Content Addressable Memory
- 주제(키워드) Binarized Neural Networks
- 발행기관 고려대학교 대학원
- 지도교수 박종선
- 발행년도 2019
- 학위수여년월 2019. 2
- 유형 Text
- 학위구분 석사
- 학과 대학원 반도체시스템공학과
- 원문페이지 39 p
- 실제URI http://www.dcollection.net/handler/korea/000000083421
- UCI I804:11009-000000083421
- DOI 10.23186/korea.000000083421.11009.0000929
- 본문언어 영어
- 제출원본 000045978512
초록/요약
Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator supporting dynamic filter size. In our proposed CAM architecture, the enormous XNOR-accumulation operation of BNN is implemented us-ing CAM search operation and time domain property. To process the whole layer effi-ciently, we determine a quantization level to process the divided 3D-filter and minimize accuracy loss with acceptable hardware overhead. Also, considering the fully parallel search of CAM and filter sliding, the parallel convolution operation for the non-overlapping filtering windows has been enabled by storing iFMAPs and applying aligned weights. To verify the effectiveness of the proposed BNN accelerator using CAM supporting 2nd-6th CONV layer of target network, the proposed work has been implemented using 65nm CMOS technology. The implementation results with HSPICE and PrimeTime-PX show that the proposed CAM based BNN accelerator achieves 84.6% energy savings with 25% area overhead, respectively. The parallel XNOR-accumulation operation in the proposed CAM also shows 85.5% processing cycle reduction.
more목차
Table of Contents i
List of Figures ii
List of Tables iii
Abstract v
1. Introduction 1
2. Preliminaries 5
2.1 Binarized Neural Network 5
2.2 Content Addressable Memory 7
3. The Proposed BNN Accclerator 10
3.1 BNN Operation based on CAM 10
3.2 Bit precision of Partial Sum and Multi-level TDA 16
3.3 Proposed Architecture Supporting Multi-layer with Parallel Operation and Memory Address Mapping 20
4. Simulation Results and Evaluation 24
4.1 Experimental Setup 24
4.2 Circuit Level Simulation Results 25
5. Conclusion 28
List of References 29
