Process development of SiO2 nanopatterns using Inductively coupled plasma
- 주제(키워드) ICP-RIE , Bulk dielectric , Capacitance , Faraday cage
- 발행기관 고려대학교 대학원
- 지도교수 주병권
- 발행년도 2018
- 학위수여년월 2018. 2
- 학위구분 석사
- 학과 대학원 전기전자공학과
- 원문페이지 64 p
- 실제URI http://www.dcollection.net/handler/korea/000000080231
- 본문언어 영어
- 제출원본 000045932536
초록/요약
ICP-RIE (Inductively Coupled Plasma – Reactive Ion Etching) is widely used in the semiconductor industry. We used ICP to etch thin substrate such as Si wafer, but we wondered if the same etch pattern appeared on bulk dielectric substrate such as thick glass substrate. The substrate used in this experiment is as follows. SiO2 was deposited on Si substrate and patterned Cr mask was fabricated by NIL and E-beam evaporator. The patterned Si substrate was placed on a quartz pedestal and the thickness and the base area of the pedestal were changed to observe the results. In the bulk dielectric substrate, the etch profile varies depending on the thickness and size of the material. Therefore, new etching conditions must be established every time to obtain the desired etching profile. A faraday cage can be used to create a uniform etch environment regardless of the bulk substrate difference there was. And the etching patterns were observed by varying ICP power, RF power, gas flow rate, and pressure.
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Contents
List of Abbreviations -------------------------------------------------------------------- 6
List of Figures -------------------------------------------------------------------- 7
List of Tables --------------------------------------------------------------------- 13
Chapter 1. Introduction ------------------------------------------------------- 14
Chapter 2. Theoretical background ----------------------------------------- 16
2. 1 ICP-RIE ----------------------------------------------------------------- 16
2. 2 SiO2 etching mechanism---------------------------------------------- 20
2. 3 Effects of process parameters ---------------------------------------- 22
Chapter 3. Experimental Details --------------------------------------------- 25
3. 1 Fabrication process ---------------------------------------------------- 25
3. 2 Plasma Etching Process ----------------------------------------------- 27
Chapter 4. Results and Discussions -------------------------------------- 31
4. 1 Effect of dielectric substrate size------------------------------------ 31
4. 2 Angled etching at edge------------------------------------------------ 37
4. 3 Effect of Faraday Cage------------------------------------------------- 40
4. 4 Effect of process parameters ----------------------------------------- 51
4.4.1 ICP power & RF power---------------------------------------- 51
4.4.2 Flow rate-------------------------------------------------------- 54
4.4.3 Pressure--------------------------------------------------------- 56
Chapter 5. Conclusions ----------------------------------------------------- 58
References ----------------------------------------------------------------------- 60
