Simulation and characterization of gate-all-around FETs for sub-10nm CMOS technologies
- 주제(키워드) Gate-all-around , Field-effect-transistor , Nanowire , Nanosheet , Ring oscillator , Transient simulation
- 발행기관 고려대학교 대학원
- 지도교수 김상식
- 발행년도 2018
- 학위수여년월 2018. 2
- 학위구분 석사
- 학과 대학원 전기전자공학과
- 세부전공 반도체 및 나노전공
- 원문페이지 55 p
- 실제URI http://www.dcollection.net/handler/korea/000000079723
- 본문언어 영어
- 제출원본 000045932550
초록/요약
In this thesis, the performance of ring oscillators composed of gate-all-around (GAA) field-effect transistors (FETs) with varying the number of nanowire (NW) channels (i.e. single, double, triple, and quadruple) and the shape of channels (i.e. wire, and sheet type), for sub-10-nm logic applications is investigated. The simulations reveal that ring oscillators with double, triple, and quadruple NW channels exhibit improvements of up to 50%, 85%, and 97%, respectively, in the oscillation frequencies (fosc), compared to a ring oscillator with a single NW channel, due to the large drive current, in spite of the increased intrinsic capacitance of a given device. Moreover, this work shows that the fosc improvement ratio of the ring oscillators becomes saturated with triple NW channels with additional load capacitances of 0.1 fF and 0.01 fF, which are similar to, or less than the intrinsic device capacitance (~0.1 fF). In addition, it is also demonstrated that the ring oscillators with 3 stacked nano-sheet type of channels with width three times wider than the state-of-the-art fin width exhibit improvements of up to 22% in the oscillation frequencies, compared to a ring oscillator with FinFETs which is industry’s the most advanced architecture in volume production. Thus, this study provides an insight for determining the optimal number of NW channels, capacitive load and the shape of channels for device development and circuit design of GAA FETs.
more목차
Chapter 1. Introduction
1.1 CMOS device scaling down
1.2 Advanced MOSFET device structures
1.3 Gate-all-around FETs
1.4 Research objectives and overview
Chapter 2. TCAD simulation method and device structures
2.1 Simulation flow and methodology
2.2 Key device parameters and structures
Chapter 3. Results and discussion
3.1 Electrical characteristics of n- and p-FETs constructing inverts and ring oscillators
3.2 Electrical characteristics of inverters
3.3 Performance of ring oscillators composed of gate-all-around FETs
Chapter 4. Conclusions
