V-I Converter-Based Voltage-Controlled Oscillator with Improved Linear Gain Characteristic in Phase-Locked Loops
- 주제(키워드) PLL , VCO
- 발행기관 고려대학교 대학원
- 지도교수 김수원
- 발행년도 2017
- 학위수여년월 2017. 2
- 학위구분 석사
- 학과 대학원 나노반도체공학과
- 세부전공 나노반도체설계전공
- 원문페이지 65 p
- 실제URI http://www.dcollection.net/handler/korea/000000072244
- 본문언어 영어
- 제출원본 000045897343
초록/요약
The phase-locked loops (PLL) is a critical part in clock synthesis systems, such as clock and data recovery and frequency synthesis. Output of PLL is the voltage-controlled-oscillator (VCO). As a result, VCO is core block in PLL. To cover wide range of data rate. PLL needs VCO, which has wide frequency tuning range. Data rate is increasing. Also, power consumption is increasing. To reduce power consumption, supply voltage is needed to be reduced. Therefore, range of control voltage (Vctrl) at VCO is also reduced. Data clock application can be operated at various frame rates. So it should have high ratio between minimum and maximum frequency. To stabilize loop characteristic of PLL. Voltage controlled oscillator should have several properties. One of them is linear gain (KVCO) over a wide control voltage (Vctrl). Others are low power, small area, and variation of supply voltage noise. output signal [1]. This paper proposes the improved V-I converter based voltage controlled oscillator (VCO) and PLL based proposed VCO. The proposed V-I converter changes voltage into current. Gain of V-I converter has linear characteristic. It is possible to achieve a linear gain (KVCO) within full range of control voltage, which is from ground to supply voltage approach at 1.8V process. It is not control supply voltage of ring oscillator but control gate of mosfet. As a result, output of VCO is full supply transition output, which has benefit for amplitude of noise. Also, it is not need additional circuits, such as a low-to-full amplifier which compensates swing of delay cell. By using the improved V-I converter, it is possible to achieve linear KVCO with a wider Vctrl range, its tuning range is changed from 1.25 to 3.6 GHz with a linear gain characteristic at VDD 1V process. Peak to peak (P2P) and root mean square (RMS) jitters of PLL are respectively 12.7ps and 2.151ps at 2.4GHz. The experimental results verify that P2P and RMS jitters over wide frequency range are almost same. The design is fabricated in 65nm CMOS technology and consumes 3.6mW from a 1V supply voltage.
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Table of Contents
1. Introduction 1
1.1 Motivation 1
1.2 Application 2
1.3 Thesis Organization 3
2. Phase Looked Loops 4
2.1 Concept of PLLs 4
2.2 Detail Blocks of PLL 5
2.3 Design of VCO 12
3. Conventional structures of VCO 15
3.1 VDD control method 15
3.1.1 VDD control method I 15
3.1.2 VDD control method II 18
3.2 Non VDD control method 20
3.2.1 Non VDD control method I 20
3.2.2 Non VDD control method II 24
3.2.3 Non VDD control method III 27
3.2.4 Non VDD control method IV 29
4. Proposed converter based VCO 32
4.1 Structure of V-I converter VCO I 32
4.2 Structure of V-I converter VCO II 34
4.3 Structure of V-V level shifter VCO 36
5. Simulation & Experimental Results 38
5.1 Simulation Results 38
5.2 Experimental Results 44
6. Conclusion 51
Bibliography 52
