A Single-ended 6T SRAM Cell with Read-Upset-Preventor in 45 nm CMOS
- 주제(키워드) SRAM Cell
- 발행기관 고려대학교 대학원
- 지도교수 박종선
- 발행년도 2013
- 학위수여년월 2013. 8
- 학위구분 석사
- 학과 공학대학원 전자·컴퓨터공학전공
- 원문페이지 32 p
- 실제URI http://www.dcollection.net/handler/korea/000000046282
- 본문언어 영어
- 제출원본 000045764493
초록/요약
This work presents a single-ended 6T SRAM cell with Read-Upset-Preventor (RUP) to overcome the read disturbance of conventional 6T SRAM cell in low voltage operation. A RUP device introduced in between PMOS and NMOS of an inverter prevents the flipping of data even in worst case, and hence, the mean of read SNM is improved by 1.92x compared with conventional 6T cell, in terms of read stability. A word line boosting technique based on capacitive-coupling is utilized to compensate for the weak-writability. Single-ended pseudo-di fferential sensing scheme with dynamic reference is employed which has higher read margin than reference bitcell and these margins are improved by 2.6x for read-0 and 1.78x for read-1. This proposed cell can work over a wide range of supply voltage from 1.1 V to 0.5 V.
more목차
Abstract
Table of Contents
List of Figures
Chapter
1 Introduction
2 Proposed Single-ended 6T SRAM Cell with RUP
3 Boosted Wordline Scheme for Compensation of Weak-Writability
4 Single-ended Sensing Scheme with Dynamic Reference
5 Statistical Simulation and Comparison Results
5.1 Cell Area Comparison
5.2 Read SNM Comparison
5.3 Bit Failure Count
5.4 Comparison between Dynamic Reference and Reference Cell
5.5 Write Time and Write Margin Comparison
6 Memory Array Organization and Layout
7 Conclusion
References
