고려대학교

초록/요약

A bolometer sensor used in an infrared thermal imaging system has many advantages on the manufacturing process. It does not need a separate cooling system and its manufacturing is easy. However, not only is the sensitivity low, but also the fixed pattern noise (FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed by using the high performance readout integrated circuit (ROIC) with noise reduction techniques, high sensitivity, superior linearity and so on. To design ROIC with high performance, important considerations should be considered as following. At first, the signal sensing mechanism should be established, because two type mechanisms which are a current mode using constant voltage and a voltage mode using constant current have merits and demerits. At second, bias value should be fixed before designing ROIC, because the sensitivity of bolometer is changed as value of voltage or current applied to the bolometer. At last, all kinds of noises made from process variation should be removed, including FPN noise. It makes difficult to detect the change of the resistance because it is very small. In our paper, we designed current mode ROIC because it is easy to manufacture and can be controlled easily although it has low sensitivity. And differential delta sampling (DDS) circuit was proposed to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of the FPN noise, the reference signal compensation circuit was proposed. This circuit can compensate the reference signal with an error due to the FPN noise by using on-resistance of MOS transistor. Also, to control bias voltage the self bias circuit was proposed. This circuit uses current mirror circuit to maintain constant voltage at one side of bolometer. A ROIC with the techniques as previously explained was designed and analyzed by HSPICE simulator. As a result of simulation, it was possible to acquire the ROIC which has higher sensitivity and noise immunity. Based on the simulation results, chip was fabricated by a standard 0.18 m CMOS process.